V1.0
This commit is contained in:
vetusmagnus
@@ -0,0 +1,579 @@
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#!/usr/bin/env python3
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"""vu_recomp.py GEN_DIR DECOMP_REPO [--dis OUT_DIR]
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Ahead-of-time translator for the game's VU microprograms (VU0 and VU1 micro
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mode). The microcode lives in the executable's .vutext section, listed by its
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.DVP.ovlytab overlay table: one entry per MPG upload (VU address, size, load
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address). Uploads of one program image share a group id in the overlay's
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name (".DVP.overlay..<vu address>.<group>.<line>.<n>").
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Each image is translated to one C function over an RcVu0 (host/include/vu.h):
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a switch on the start address, then one labelled piece of C per instruction
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pair. The function is compiled with the rest of the host program; nothing is
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decoded at run time. Images that fit VU0's 4 KB micro memory are translated
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for both VUs, the rest for VU1 only. The bytes of every upload are kept too,
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so the runtime (host/src/gfx/vu.c) can tell which image is in micro memory
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after the game's MPG uploads.
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Semantics kept:
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- upper and lower ops of a pair both read the registers as they were before
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the pair; the upper op's result wins when both write the same register;
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with the I bit the lower word is LOI's immediate (the pair's own upper
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op still reads the old I: the game's sine code depends on it).
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- branches and E (end) have one delay slot pair.
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- FMAC results that overflow are +-MAX, as on the VU (which has no inf
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or NaN): x86 would give inf, and then NaN (inf * 0, inf - inf), where
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the VU keeps finite numbers (vu_fc).
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- MAC/status/clip flags reach FSAND/FMAND/FCAND... 4 cycles after the op
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issues, Q 7 cycles after DIV/SQRT and 13 after RSQRT: the code counts
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cycles, including the stalls on VF registers that are still being written
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(4-cycle latency, per component), which are worked out here.
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Writes GEN_DIR/vu_prog_<n>.c (one per image and VU) and GEN_DIR/vu_table.c.
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"""
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import os, re, struct, sys
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sys.path.insert(0, os.path.dirname(os.path.abspath(__file__)))
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from vu_isa import decode_pair, BRANCHES, XYZW
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GEN, REPO = sys.argv[1], sys.argv[2]
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DIS = sys.argv[sys.argv.index("--dis") + 1] if "--dis" in sys.argv else None
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EXE = os.environ.get("UYA_EXE") or os.path.join(REPO, "baserom", "SCES_509.16") # build.py: the copy read from the disc image
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img = open(EXE, "rb").read()
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# ---- the executable's sections ------------------------------------------------
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e_shoff, = struct.unpack_from("<I", img, 0x20)
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shentsize, shnum, shstrndx = struct.unpack_from("<HHH", img, 0x2E)
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secs = [struct.unpack_from("<10I", img, e_shoff + i * shentsize) for i in range(shnum)]
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strtab_off = secs[shstrndx][4]
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def secname(s):
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o = strtab_off + s[0]
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return img[o:img.index(b"\0", o)].decode()
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bysec = {secname(s): s for s in secs}
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vutext = bysec[".vutext"]
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VT_ADDR, VT_OFF, VT_SIZE = vutext[3], vutext[4], vutext[5]
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tab = bysec[".DVP.ovlytab"]
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ostr = bysec[".DVP.ovlystrtab"]
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tabd = img[tab[4]:tab[4] + tab[5]]
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strd = img[ostr[4]:ostr[4] + ostr[5]]
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groups = {}
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order = []
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for k in range(0, len(tabd) // 12 * 12, 12):
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no, lma, vma = struct.unpack_from("<3I", tabd, k)
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name = strd[no:strd.index(b"\0", no)].decode()
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size = bysec[name][5]
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parts = name.split(".") # ['', 'DVP', 'overlay', '', '0x0', group, line, n]
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g = parts[5]
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o = VT_OFF + (lma - VT_ADDR)
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data = img[o:o + size]
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if g not in groups:
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groups[g] = []
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order.append(g)
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groups[g].append((vma, data))
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# ---- register use (for stalls) ------------------------------------------------
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def up_rw(u):
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"""VF (reg, comp) read and written by an upper op"""
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r, w = [], []
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k = u.kind
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if k in ("nop", "bad"):
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return r, w
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if k == "arith":
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for c in u.comps:
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r.append((u.fs, c))
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if u.bc in ("x", "y", "z", "w"):
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r.append((u.ft, XYZW.index(u.bc)))
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elif u.bc is None:
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r.append((u.ft, c))
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if not u.acc:
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w.append((u.fd, c))
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elif k in ("opmula", "opmsub"):
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for c in (0, 1, 2):
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r += [(u.fs, c), (u.ft, c)]
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if k == "opmsub":
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w += [(u.fd, c) for c in u.comps if c < 3]
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elif k in ("itof", "ftoi", "abs"):
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r += [(u.fs, c) for c in u.comps]
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w += [(u.ft, c) for c in u.comps]
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elif k == "clip":
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r += [(u.fs, 0), (u.fs, 1), (u.fs, 2), (u.ft, 3)]
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return r, w
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def lo_rw(l):
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r, w = [], []
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if l is None:
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return r, w
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n = l.name
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if n in ("lq", "lqi", "lqd"):
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w += [(l.ft, c) for c in l.comps]
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elif n in ("sq", "sqi", "sqd"):
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r += [(l.fs, c) for c in l.comps]
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elif n == "move":
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r += [(l.fs, c) for c in l.comps]
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w += [(l.ft, c) for c in l.comps]
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elif n == "mr32":
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r += [(l.fs, (c + 1) & 3) for c in l.comps]
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w += [(l.ft, c) for c in l.comps]
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elif n == "mtir":
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r.append((l.fs, l.fsf))
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elif n == "mfir":
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w += [(l.ft, c) for c in l.comps]
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elif n == "div":
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r += [(l.fs, l.fsf), (l.ft, l.ftf)]
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elif n == "sqrt":
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r.append((l.ft, l.ftf))
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elif n == "rsqrt":
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r += [(l.fs, l.fsf), (l.ft, l.ftf)]
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return [x for x in r if x[0]], [x for x in w if x[0]]
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FLAG_UPPER = {"add", "sub", "mul", "madd", "msub", "adda", "suba", "mula", "madda", "msuba"}
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class Image:
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def __init__(self, gid, blocks, vu):
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self.gid, self.blocks, self.vu = gid, sorted(blocks), vu
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self.mem = {}
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for vma, data in self.blocks:
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for k in range(0, len(data), 8):
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self.mem[vma + k] = struct.unpack_from("<II", data, k)
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self.warn = []
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def dis_image(im, out):
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with open(out, "w") as f:
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for pc in sorted(im.mem):
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lo, hi = im.mem[pc]
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u, l, fl, imm = decode_pair(lo, hi)
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fs = "".join(x for x in "IEMDT" if fl[x])
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ls = "loi %08X" % imm if imm is not None else l.text()
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f.write("%04X %-3s %-45s | %s\n" % (pc, fs, u.text(), ls))
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# ---- translation ----------------------------------------------------------------
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def gen_image(im):
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vu = im.vu
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MEM = "VU%d_MEM" % vu
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PCMASK = 0x3FF8 if vu == 1 else 0xFF8
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pcs = sorted(im.mem)
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dec = {}
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for pc in pcs:
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lo, hi = im.mem[pc]
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dec[pc] = decode_pair(lo, hi)
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reads_sm = any(d[1] is not None and d[1].name in ("fsand", "fsor", "fseq", "fmand", "fmor", "fmeq") for d in dec.values())
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# ---- static cycles: stalls on VF registers still being written ----
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stall, qstall = {}, {}
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ready, t, qready = {}, 0, None
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prev_end = True
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for pc in pcs:
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u, l, fl, imm = dec[pc]
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if prev_end or (pc - 8) not in dec:
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ready, t, qready = {}, 0, None
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ti = t + 1
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r1, w1 = up_rw(u)
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r2, w2 = lo_rw(l)
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need = max([ready.get(x, 0) for x in r1 + r2] + [0])
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s = max(0, need - ti)
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ti += s
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qs = 0
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if l is not None and l.name in ("waitq", "div", "sqrt", "rsqrt") and qready is not None and qready > ti:
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qs = qready - ti
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ti += qs
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if l is not None and l.name in ("div", "sqrt", "rsqrt"):
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qready = ti + (13 if l.name == "rsqrt" else 7)
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stall[pc] = s + qs
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for x in w1 + w2:
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ready[x] = ti + 4
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t = ti
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# a new straight-line run starts after an unconditional jump's or E's delay slot
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prev_end = False
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p = pc - 8
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if p in dec:
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pu, pl, pf, pimm = dec[p]
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if pf["E"] or (pl is not None and pl.name in ("b", "jr")):
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prev_end = True
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used_q = False
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# ---- branch VI delay: a conditional branch (or JR/JALR) whose VI register
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# was written by the instruction right before it reads the value the
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# register had before that write (before the earliest of a run of such
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# writes, up to 4 back), unless the branch stalls or the write reads flags
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# (FCAND and friends). This is the hardware's integer pipeline; PCSX2's
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# microVU models it the same way (analyzeBranchVI). ----
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FLAGREAD = {"fcand", "fcor", "fceq", "fcget", "fsand", "fsor", "fseq", "fmand", "fmor", "fmeq"}
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def vi_written(lw):
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if lw is None: return 0
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n = lw.name
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if n in ("iadd", "isub", "iand", "ior"): return lw.id_ & 15
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if n in ("iaddi", "iaddiu", "isubiu", "ilw", "ilwr", "mtir", "xtop", "xitop", "bal", "jalr"): return lw.it & 15
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if n in ("lqi", "lqd"): return lw.is_ & 15
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if n in ("sqi", "sqd"): return lw.it & 15
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return 0
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targets = set()
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for pc_ in pcs:
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l_ = dec[pc_][1]
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if l_ is not None and l_.name in ("b", "bal", "ibeq", "ibne", "ibltz", "ibgtz", "iblez", "ibgez"):
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targets.add((pc_ + 8 + l_.imm * 8) & PCMASK)
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vib_save, vib_use = {}, {}
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for pc_ in pcs:
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l_ = dec[pc_][1]
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if l_ is None or l_.name not in ("ibeq", "ibne", "ibltz", "ibgtz", "iblez", "ibgez", "jr", "jalr"): continue
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if stall[pc_] or pc_ in targets: continue
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regs = [l_.is_ & 15] + ([l_.it & 15] if l_.name in ("ibeq", "ibne") else [])
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for x in regs:
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if not x: continue
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p_ = pc_ - 8
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if p_ not in dec or dec[p_][1] is None or dec[p_][1].name in FLAGREAD or vi_written(dec[p_][1]) != x: continue
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j_ = p_
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for k_ in range(3):
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q_ = j_ - 8
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if j_ in targets or q_ not in dec or stall[j_]: break
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lq_ = dec[q_][1]
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if lq_ is None or lq_.name in FLAGREAD or vi_written(lq_) != x: break
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j_ = q_
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vib_save[j_] = x
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vib_use[pc_] = x
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break
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def VI(r):
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r &= 15
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return "0u" if r == 0 else "v->vi[%d]" % r
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def setvi(r, e):
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r &= 15
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return "" if r == 0 else "v->vi[%d] = (%s) & 0xFFFF;" % (r, e)
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def U32(r):
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return "((u32 *)v->vf[%d])" % r
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def upper(pc, u):
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"""(compute, commit) code for the upper op"""
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nonlocal used_q
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k = u.kind
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if k == "nop":
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return "", ""
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if k == "bad":
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im.warn.append("%04X upper %s" % (pc, u.name))
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return 'vu_bad(%d, 0x%04X, "%s");' % (vu, pc, u.name), ""
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comp, commit = [], []
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F = lambda r, c: "v->vf[%d][%d]" % (r, c)
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if k == "arith":
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base = u.base if u.acc else u.name
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if u.bc == "q":
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used_q = True
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comp.append("f32 qv = vu_q(v, cyc);")
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def B(c):
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if u.bc in ("x", "y", "z", "w"): return F(u.ft, XYZW.index(u.bc))
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if u.bc == "q": return "qv"
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if u.bc == "i": return "v->i"
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return F(u.ft, c)
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for c in u.comps:
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a, b = F(u.fs, c), B(c)
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e = {"add": "%s + %s" % (a, b), "sub": "%s - %s" % (a, b), "mul": "%s * %s" % (a, b),
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"madd": "v->acc[%d] + vu_fc(%s * %s)" % (c, a, b), "msub": "v->acc[%d] - vu_fc(%s * %s)" % (c, a, b),
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"max": "fmaxf(%s, %s)" % (a, b), "mini": "fminf(%s, %s)" % (a, b)}[base]
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comp.append("f32 u%d = %s;" % (c, e))
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for c in u.comps:
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if u.acc: commit.append("v->acc[%d] = vu_fc(u%d);" % (c, c))
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elif u.fd: commit.append("v->vf[%d][%d] = vu_fc(u%d);" % (u.fd, c, c))
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if reads_sm and base in ("add", "sub", "mul", "madd", "msub"):
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commit.append("vu_fl_push(v, cyc, %s);" % (" | ".join("vu_macbits(u%d, %d)" % (c, c) for c in u.comps) or "0"))
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elif k in ("opmula", "opmsub"):
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ex = {0: (1, 2), 1: (2, 0), 2: (0, 1)}
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cs = [c for c in u.comps if c < 3]
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for c in cs:
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a, b = ex[c]
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p = "%s * %s" % (F(u.fs, a), F(u.ft, b))
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comp.append("f32 u%d = %s;" % (c, p if k == "opmula" else "v->acc[%d] - vu_fc(%s)" % (c, p)))
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for c in cs:
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if k == "opmula": commit.append("v->acc[%d] = vu_fc(u%d);" % (c, c))
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elif u.fd: commit.append("v->vf[%d][%d] = vu_fc(u%d);" % (u.fd, c, c))
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if reads_sm:
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commit.append("vu_fl_push(v, cyc, %s);" % (" | ".join("vu_macbits(u%d, %d)" % (c, c) for c in cs) or "0"))
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elif k == "itof":
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for c in u.comps:
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comp.append("u32 n%d = vu_itof(%s[%d], %.9ef);" % (c, U32(u.fs), c, 1.0 / (1 << u.shift)))
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if u.ft:
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commit += ["%s[%d] = n%d;" % (U32(u.ft), c, c) for c in u.comps]
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elif k == "ftoi":
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for c in u.comps:
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comp.append("s32 n%d = vu_ftoi(%s, %.1ff);" % (c, F(u.fs, c), float(1 << u.shift)))
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if u.ft:
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commit += ["%s[%d] = (u32)n%d;" % (U32(u.ft), c, c) for c in u.comps]
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elif k == "abs":
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for c in u.comps:
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comp.append("u32 n%d = %s[%d] & 0x7FFFFFFFu;" % (c, U32(u.fs), c))
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if u.ft:
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commit += ["%s[%d] = n%d;" % (U32(u.ft), c, c) for c in u.comps]
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elif k == "clip":
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comp.append("f32 cw = v->vf[%d][3];" % u.ft)
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comp.append("f32 cs[3] = { v->vf[%d][0], v->vf[%d][1], v->vf[%d][2] };" % (u.fs, u.fs, u.fs))
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commit.append("vu_clipw(v, cyc, cs, cw);")
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return " ".join(comp), " ".join(commit)
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def lower(pc, l):
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"""(pre, code, kind, target) ; kind in None, 'b' (static target), 'j' (npc)"""
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nonlocal used_q
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n = l.name
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c0 = l.comps[0] if l.comps else 0
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if n.startswith("?"):
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im.warn.append("%04X lower %s" % (pc, n))
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return "", 'vu_bad(%d, 0x%04X, "%s");' % (vu, pc, n), None, None
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if n == "move":
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if not l.comps or not l.ft: return "", "", None, None
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return "", " ".join("%s[%d] = %s[%d];" % (U32(l.ft), c, U32(l.fs), c) for c in l.comps), None, None
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if n == "mr32":
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if not l.ft: return "", "", None, None
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s = "{ u32 m0 = %s[1], m1 = %s[2], m2 = %s[3], m3 = %s[0]; " % (U32(l.fs), U32(l.fs), U32(l.fs), U32(l.fs))
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return "", s + " ".join("%s[%d] = m%d;" % (U32(l.ft), c, c) for c in l.comps) + " }", None, None
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if n in ("lq", "lqi", "lqd"):
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reg = l.is_
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pre = setvi(reg, VI(reg) + " - 1") + " " if n == "lqd" else ""
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post = " " + setvi(reg, VI(reg) + " + 1") if n == "lqi" else ""
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addr = VI(reg) + (" + %d" % l.imm if n == "lq" else "")
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body = " ".join("%s[%d] = m[%d];" % (U32(l.ft), c, c) for c in l.comps) if l.ft else ""
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return "", "%s{ const u32 *m = %s(%s); %s }%s" % (pre, MEM, addr, body, post), None, None
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if n in ("sq", "sqi", "sqd"):
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reg = l.it
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||||
pre = setvi(reg, VI(reg) + " - 1") + " " if n == "sqd" else ""
|
||||
post = " " + setvi(reg, VI(reg) + " + 1") if n == "sqi" else ""
|
||||
addr = VI(reg) + (" + %d" % l.imm if n == "sq" else "")
|
||||
body = " ".join("m[%d] = %s[%d];" % (c, U32(l.fs), c) for c in l.comps)
|
||||
return "", "%s{ u32 *m = %s(%s); %s }%s" % (pre, MEM, addr, body, post), None, None
|
||||
if n in ("ilw", "ilwr"):
|
||||
addr = VI(l.is_) + (" + %d" % l.imm if n == "ilw" else "")
|
||||
return "", setvi(l.it, "%s(%s)[%d]" % (MEM, addr, c0)), None, None
|
||||
if n in ("isw", "iswr"):
|
||||
addr = VI(l.is_) + (" + %d" % l.imm if n == "isw" else "")
|
||||
return "", "{ u32 *m = %s(%s); %s }" % (MEM, addr, " ".join("m[%d] = %s;" % (c, VI(l.it)) for c in l.comps)), None, None
|
||||
if n in ("iadd", "isub", "iand", "ior"):
|
||||
op = {"iadd": "+", "isub": "-", "iand": "&", "ior": "|"}[n]
|
||||
return "", setvi(l.id_, "%s %s %s" % (VI(l.is_), op, VI(l.it))), None, None
|
||||
if n == "iaddi":
|
||||
return "", setvi(l.it, "%s + (%d)" % (VI(l.is_), l.imm)), None, None
|
||||
if n == "iaddiu":
|
||||
return "", setvi(l.it, "%s + %d" % (VI(l.is_), l.imm)), None, None
|
||||
if n == "isubiu":
|
||||
return "", setvi(l.it, "%s - %d" % (VI(l.is_), l.imm)), None, None
|
||||
if n == "mtir":
|
||||
return "", setvi(l.it, "%s[%d]" % (U32(l.fs), l.fsf)), None, None
|
||||
if n == "mfir":
|
||||
if not l.ft: return "", "", None, None
|
||||
return "", " ".join("%s[%d] = (u32)(s32)(s16)%s;" % (U32(l.ft), c, VI(l.is_)) for c in l.comps), None, None
|
||||
F = lambda r, c: "v->vf[%d][%d]" % (r, c)
|
||||
if n == "div":
|
||||
used_q = True
|
||||
return "cyc = vu_qwait(v, cyc);", "vu_qset(v, cyc, 7, vu_div(%s, %s));" % (F(l.fs, l.fsf), F(l.ft, l.ftf)), None, None
|
||||
if n == "sqrt":
|
||||
used_q = True
|
||||
return "cyc = vu_qwait(v, cyc);", "vu_qset(v, cyc, 7, vu_sqrt(%s));" % F(l.ft, l.ftf), None, None
|
||||
if n == "rsqrt":
|
||||
used_q = True
|
||||
return "cyc = vu_qwait(v, cyc);", "vu_qset(v, cyc, 13, vu_rsqrt(%s, %s));" % (F(l.fs, l.fsf), F(l.ft, l.ftf)), None, None
|
||||
if n == "waitq":
|
||||
return "cyc = vu_qwait(v, cyc);", "", None, None
|
||||
if n == "fcand": return "", setvi(1, "(vu_clip(v, cyc) & 0x%X) != 0" % l.imm), None, None
|
||||
if n == "fcor": return "", setvi(1, "((vu_clip(v, cyc) | 0x%X) & 0xFFFFFF) == 0xFFFFFF" % l.imm), None, None
|
||||
if n == "fceq": return "", setvi(1, "(vu_clip(v, cyc) & 0xFFFFFF) == 0x%X" % l.imm), None, None
|
||||
if n == "fcset": return "", "vu_fcset(v, cyc, 0x%X);" % l.imm, None, None
|
||||
if n == "fcget": return "", setvi(l.it, "vu_clip(v, cyc) & 0xFFF"), None, None
|
||||
if n == "fsand": return "", setvi(l.it, "vu_status(v, cyc) & 0x%X" % l.imm), None, None
|
||||
if n == "fsor": return "", setvi(l.it, "vu_status(v, cyc) | 0x%X" % l.imm), None, None
|
||||
if n == "fseq": return "", setvi(l.it, "(vu_status(v, cyc) & 0xFFF) == 0x%X" % l.imm), None, None
|
||||
if n == "fsset": return "", "vu_fsset(v, cyc, 0x%X);" % l.imm, None, None
|
||||
if n == "fmand": return "", setvi(l.it, "%s & vu_mac(v, cyc)" % VI(l.is_)), None, None
|
||||
if n == "fmor": return "", setvi(l.it, "%s | vu_mac(v, cyc)" % VI(l.is_)), None, None
|
||||
if n == "fmeq": return "", setvi(l.it, "(%s & 0xFFFF) == vu_mac(v, cyc)" % VI(l.is_)), None, None
|
||||
if n == "xgkick":
|
||||
if vu != 1:
|
||||
im.warn.append("%04X xgkick on VU0" % pc)
|
||||
return "", 'vu_bad(0, 0x%04X, "xgkick");' % pc, None, None
|
||||
return "", "vu_xgkick(%s);" % VI(l.is_), None, None
|
||||
if n == "xtop": return "", setvi(l.it, "vu_vif_top(%d)" % vu), None, None
|
||||
if n == "xitop": return "", setvi(l.it, "vu_vif_itop(%d)" % vu), None, None
|
||||
if n in BRANCHES:
|
||||
link = (pc + 16) // 8
|
||||
if n == "b":
|
||||
return "", "", "b", (pc + 8 + l.imm * 8) & PCMASK
|
||||
if n == "bal":
|
||||
return "", setvi(l.it, "%d" % link), "b", (pc + 8 + l.imm * 8) & PCMASK
|
||||
JV = "vib" if vib_use.get(pc) == (l.is_ & 15) else VI(l.is_)
|
||||
if n == "jr":
|
||||
return "", "npc = (%s << 3) & 0x%X;" % (JV, PCMASK), "j", None
|
||||
if n == "jalr":
|
||||
return "", "npc = (%s << 3) & 0x%X; %s" % (JV, PCMASK, setvi(l.it, "%d" % link)), "j", None
|
||||
BV = (lambda r: "vib" if vib_use.get(pc) == (r & 15) else VI(r))
|
||||
cond = {"ibeq": "%s == %s" % (BV(l.it), BV(l.is_)), "ibne": "%s != %s" % (BV(l.it), BV(l.is_)),
|
||||
"ibltz": "(s16)%s < 0" % BV(l.is_), "ibgtz": "(s16)%s > 0" % BV(l.is_),
|
||||
"iblez": "(s16)%s <= 0" % BV(l.is_), "ibgez": "(s16)%s >= 0" % BV(l.is_)}[n]
|
||||
return "", "bt = %s;" % cond, "c", (pc + 8 + l.imm * 8) & PCMASK
|
||||
im.warn.append("%04X lower %s not translated" % (pc, n))
|
||||
return "", 'vu_bad(%d, 0x%04X, "%s");' % (vu, pc, n), None, None
|
||||
|
||||
def pair(pc):
|
||||
"""C for one pair; returns (code, flow kind, target)"""
|
||||
u, l, fl, imm = dec[pc]
|
||||
out = ["VU_TRACE(0x%04X); cyc += %d;" % (pc, 1 + stall[pc])]
|
||||
if pc in vib_save: out.append("vib = %s;" % VI(vib_save[pc]))
|
||||
uc, ucommit = upper(pc, u)
|
||||
pre = code = ""
|
||||
kind = tgt = None
|
||||
if l is not None:
|
||||
pre, code, kind, tgt = lower(pc, l)
|
||||
if pre: out.append(pre)
|
||||
if imm is not None: # LOI: the pair's upper op still reads the old I
|
||||
code = "v->i = vu_f(0x%08Xu);" % imm
|
||||
if uc or ucommit:
|
||||
out.append("{ %s %s %s }" % (uc, code, ucommit))
|
||||
elif code:
|
||||
out.append(code)
|
||||
return " ".join(x for x in out if x), kind, tgt, fl["E"]
|
||||
|
||||
body = []
|
||||
lab = lambda pc: "L_%04X" % pc
|
||||
import re as _re
|
||||
def idle(pc): # a pair that does nothing but count its cycle
|
||||
c_, k_, t_, e_ = pair(pc)
|
||||
return k_ is None and not e_ and not _re.sub(r"VU_TRACE\(0x[0-9A-F]+\);|cyc \+= \d+;|\s", "", c_)
|
||||
for pc in pcs:
|
||||
code, kind, tgt, ebit = pair(pc)
|
||||
body.append("%s: %s" % (lab(pc), code))
|
||||
nxt = pc + 8
|
||||
if kind is None and not ebit:
|
||||
if nxt not in dec:
|
||||
body.append(" vu_bad(%d, 0x%04X, \"ran off the end\"); goto done;" % (vu, nxt))
|
||||
continue
|
||||
# a branch or the end: its delay slot pair runs here as well
|
||||
if nxt in dec:
|
||||
dcode, dkind, dtgt, debit = pair(nxt)
|
||||
if dkind is not None:
|
||||
im.warn.append("%04X branch in a delay slot (ignored)" % nxt)
|
||||
if debit and not ebit:
|
||||
im.warn.append("%04X E bit in a branch delay slot" % nxt)
|
||||
body.append(" /* delay slot */ " + dcode)
|
||||
else:
|
||||
im.warn.append("%04X delay slot outside the image" % pc)
|
||||
if ebit:
|
||||
if kind is not None:
|
||||
im.warn.append("%04X branch with the E bit" % pc)
|
||||
body.append(" v->tpc = 0x%04X; goto done;" % ((pc + 16) & PCMASK))
|
||||
continue
|
||||
if kind == "b" and tgt == pc - 16 and tgt in dec and pair(tgt)[1] == "c" and idle(tgt + 8) and (nxt not in dec or idle(nxt)) \
|
||||
and "vi[" in pair(tgt)[0] and not _re.search(r"vf\[|acc\[|VU\d_MEM", pair(tgt)[0]):
|
||||
# a wait loop on a VI register the EE writes (ctc2): park here and
|
||||
# let the EE resume the program (rc_vu0_resume) when it writes one
|
||||
body.append(" v->tpc = 0x%04X; v->susp = 1; goto done; /* wait for the EE */" % tgt)
|
||||
elif kind == "b":
|
||||
body.append(" goto %s;" % lab(tgt) if tgt in dec else " pc = 0x%04X; goto dispatch;" % tgt)
|
||||
elif kind == "c":
|
||||
body.append(" if (bt) %s" % ("goto %s;" % lab(tgt) if tgt in dec else "{ pc = 0x%04X; goto dispatch; }" % tgt))
|
||||
if nxt + 8 in dec:
|
||||
body.append(" goto %s;" % lab(nxt + 8))
|
||||
else:
|
||||
body.append(" goto done;")
|
||||
elif kind == "j":
|
||||
body.append(" pc = npc; goto dispatch;")
|
||||
|
||||
name = "vup_%s_vu%d" % (im.gid, vu)
|
||||
out = ["/* VU%d microprogram image %s, translated from the executable by tools/vu_recomp.py */" % (vu, im.gid),
|
||||
'#include "vu.h"', "",
|
||||
"void %s(RcVu0 *v, u32 pc)" % name, "{",
|
||||
" u32 cyc = 0, npc = 0, vib = 0; int bt = 0; (void)npc; (void)bt; (void)vib;",
|
||||
" v->st_int = v->status; v->cl_int = v->clip;",
|
||||
"dispatch:",
|
||||
" switch (pc & 0x%X) {" % PCMASK]
|
||||
for pc in pcs:
|
||||
out.append(" case 0x%04X: goto %s;" % (pc, lab(pc)))
|
||||
out.append(' default: vu_bad(%d, pc, "start address"); goto done;' % vu)
|
||||
out.append(" }")
|
||||
out += body
|
||||
out += ["done:", " vu_settle(v);", "}"]
|
||||
return name, "\n".join(out) + "\n"
|
||||
|
||||
|
||||
def extra_images():
|
||||
"""Microcode the game uploads that is not in .vutext (none is known for
|
||||
RAC1): the runtime reports such an upload and, with UYA_VUDUMP=dir, saves
|
||||
it as vu<N>_<addr>_<hash>.bin. Files of that name in RAC1_VU_EXTRA (or
|
||||
the vu_extra folder next to build.py) are translated as images of their
|
||||
own, one upload each."""
|
||||
d = os.environ.get("RAC1_VU_EXTRA") or os.path.join(os.path.dirname(os.path.dirname(os.path.abspath(__file__))), "vu_extra")
|
||||
out = []
|
||||
if not os.path.isdir(d):
|
||||
return out
|
||||
for fn in sorted(os.listdir(d)):
|
||||
m = re.fullmatch(r"vu([01])_([0-9A-Fa-f]{4})_([0-9A-Fa-f]{8})\.bin", fn)
|
||||
if not m:
|
||||
continue
|
||||
data = open(os.path.join(d, fn), "rb").read()
|
||||
data = data[:len(data) // 8 * 8]
|
||||
out.append(Image("x%s_%s" % (m.group(2).upper(), m.group(3).upper()), [(int(m.group(2), 16), data)], int(m.group(1))))
|
||||
return out
|
||||
|
||||
|
||||
def main():
|
||||
os.makedirs(GEN, exist_ok=True)
|
||||
images = []
|
||||
for g in order:
|
||||
blocks = groups[g]
|
||||
size = max(vma + len(d) for vma, d in blocks)
|
||||
kicks = any(decode_pair(*struct.unpack_from("<II", d, k))[1] is not None and
|
||||
decode_pair(*struct.unpack_from("<II", d, k))[1].name == "xgkick"
|
||||
for vma, d in blocks for k in range(0, len(d), 8))
|
||||
# XGKICK only exists on VU1; anything bigger than 4 KB is VU1 code too
|
||||
for vu in ((0, 1) if size <= 0x1000 and not kicks else (1,)):
|
||||
images.append(Image(g, blocks, vu))
|
||||
images += extra_images()
|
||||
if DIS:
|
||||
os.makedirs(DIS, exist_ok=True)
|
||||
for im in images:
|
||||
if im.vu == 1 or len([i for i in images if i.gid == im.gid]) == 1:
|
||||
dis_image(im, os.path.join(DIS, "%s.txt" % im.gid))
|
||||
tbl = ['/* VU microprogram images (tools/vu_recomp.py) */', '#include "vu.h"', "",
|
||||
"typedef struct { u32 vma, size; const u32 *words; } VuBlock;",
|
||||
"typedef struct { const char *name; int vu; void (*fn)(RcVu0 *, u32); int nblk; const VuBlock *blk; } VuImage;", ""]
|
||||
names = []
|
||||
nwarn = 0
|
||||
for im in images:
|
||||
name, src = gen_image(im)
|
||||
path = os.path.join(GEN, "%s.c" % name)
|
||||
old = open(path).read() if os.path.exists(path) else None
|
||||
if old != src:
|
||||
open(path, "w").write(src)
|
||||
tbl.append("void %s(RcVu0 *, u32);" % name)
|
||||
for vma, d in im.blocks:
|
||||
ws = struct.unpack("<%dI" % (len(d) // 4), d)
|
||||
tbl.append("static const u32 %s_b%04X[%d] = {" % (name, vma, len(ws)))
|
||||
for k in range(0, len(ws), 8):
|
||||
tbl.append(" " + ", ".join("0x%08X" % x for x in ws[k:k + 8]) + ",")
|
||||
tbl.append("};")
|
||||
tbl.append("static const VuBlock %s_blk[] = { %s };" % (name, ", ".join(
|
||||
"{ 0x%04X, 0x%X, %s_b%04X }" % (vma, len(d), name, vma) for vma, d in im.blocks)))
|
||||
names.append((name, im))
|
||||
for w in im.warn:
|
||||
nwarn += 1
|
||||
print("vu_recomp: image %s VU%d: %s" % (im.gid, im.vu, w))
|
||||
tbl.append("const VuImage vu_images[] = {")
|
||||
for name, im in names:
|
||||
tbl.append(' { "%s", %d, %s, %d, %s_blk },' % (im.gid, im.vu, name, len(im.blocks), name))
|
||||
tbl.append("};")
|
||||
tbl.append("const int vu_image_count = %d;" % len(names))
|
||||
src = "\n".join(tbl) + "\n"
|
||||
path = os.path.join(GEN, "vu_table.c")
|
||||
if not os.path.exists(path) or open(path).read() != src:
|
||||
open(path, "w").write(src)
|
||||
print("vu_recomp: %d microprogram images (%d pairs) translated, %d warnings" % (
|
||||
len(names), sum(len(im.mem) for _, im in names), nwarn))
|
||||
|
||||
|
||||
main()
|
||||
Reference in New Issue
Block a user